NLP-FPGA - Hardware NLP coprocessor

Keywords: reconfigurable NLP-coprocessor, field programmable gate array
Contact Person: Martin Rajman
Phone: (+41 21) 693-5277

Project Description

The general framework of this project is to build a reconfigurable NLP co-processor implemented in the form of a "Field Programmable Gate Array" (FPGA).

More precisely, the objective is to realize an FPGA-based hardware implementaion of the probabilistic (CYK-based) parsing algorithm that has been developped in the framework of the NLP activity at LIA, and to test the efficiency of such an implementation in the framework of a continuous speech recognizer.

This project is funded by grant FNRS #21-52689.97.

Last modified: Mon Apr 17 14:40:59 2000